Flip Flops
Flip flop is a sequential circuit which generally samples its inputs and changes its outputs only at particular instants of time and not continuously. Flip flop is said to be edge sensitive or edge triggered rather than being level triggered like latches.
There are 4 types -
There are 4 types -
- S-R Flip Flop
- J-K Flip Flop
- D Flip Flop
- T Flip Flop
S-R Flip Flop
It is basically S-R latch using NAND gates with an additional enable input. It is also called as level triggered SR-FF. For this, circuit in output will take place if and only if the enable input (E) is made active. In short this circuit will operate as an S-R latch if E = 1 but there is no change in the output if E = 0.
Master Slave JK Flip Flop
Master slave JK FF is a cascade of two S-R FF with feedback from the output of second to input of first. Master is a positive level triggered. But due to the presence of the inverter in the clock line, the slave will respond to the negative level. Hence when the clock = 1 (positive level) the master is active and the slave is inactive. Whereas when clock = 0 (low level) the slave is active and master is inactive.
Delay Flip Flop / D Flip Flop
Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected between S and R inputs. It has only one input. The input data is appearing at the output after some time. Due to this data delay between i/p and o/p, it is called delay flip flop. S and R will be the complements of each other due to NAND inverter. Hence S = R = 0 or S = R = 1, these input condition will never appear. This problem is avoid by SR = 00 and SR = 1 conditions.
Toggle Flip Flop / T Flip Flop
Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected together. It has only input denoted by T as shown in the Symbol Diagram. The symbol for positive edge triggered T flip flop is shown in the Block Diagram.
Applications of flip flop
Level triggered flip flop:-it is a flip flop where output changes when clock =1.
Edge triggered flip flop:-it is a flip flop which changes output at positive edge of the clock.
Negative edge triggered flip flop:-it is a flip flop which changes output at negative edge of the clock.
It is used in:
Edge triggered flip flop:-it is a flip flop which changes output at positive edge of the clock.
Negative edge triggered flip flop:-it is a flip flop which changes output at negative edge of the clock.
It is used in:
- Counters
- State Machine.
- Shift register.